Digital Design Validation Specialist

8 hours ago

Tel AvivYafo, Israel beBeeVerification Full time
Formal Verification Expert

We are seeking an experienced Formal Verification Engineer to join our team. In this role, you will be responsible for planning and executing the formal verification strategy for digital design blocks.

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  • Plan the formal verification strategy and create properties and constraints for digital design blocks.
  • Utilize formal property verification tools combined with formal verification closure techniques to verify properties.
  • Contribute improvements to methodologies to enhance formal verification results.
  • Architect and implement reusable formal verification components.

Key Responsibilities:

Our ideal candidate will have a strong background in formal verification and experience working with digital design blocks. They will also possess excellent problem-solving skills and be able to communicate complex technical ideas effectively.

">About Us

At Google, we are committed to innovation and pushing boundaries. Our team is dedicated to developing custom silicon solutions that power the future of direct-to-consumer products. We are passionate about creating hardware experiences that deliver unparalleled performance, efficiency, and integration.

">What You'll Do

As a Formal Verification Engineer, you will contribute to the development of cutting-edge formal verification strategies and methodologies. You will work closely with cross-functional teams to identify and address formal verification challenges, and develop creative solutions to enhance formal verification results.

">Requirements

To be successful in this role, you must have a deep understanding of formal verification concepts and principles. You should also have excellent communication and collaboration skills, as well as the ability to work effectively in a fast-paced environment.

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Experience Requirements:

* Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.* 4 years of experience working in main interconnects, Direct Memory Access (DMA), controllers, and power management.* Experience capturing design specification in a temporal assertion language (e.g., System Verilog Assertions (SVA) or Property Specification Language (PSL)).* Master's degree or PhD in Electrical Engineering or Computer Science, or a related field.* Experience working with one or more formal verification tools (e.g., JasperGold, VC Formal, Questa Formal, or Display and Video 360).

">Preferred Qualifications

* Experience working on large-scale digital design projects.* Strong knowledge of digital design blocks and their interactions.* Excellent problem-solving and analytical skills.* Ability to communicate complex technical ideas effectively.* Strong collaboration and teamwork skills.

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