Physical Design Engineer, Full Chip Layout

1 week ago

Tel Aviv, Tel Aviv, Israel Google Full time $150,000 - $200,000 per year
Minimum qualifications:
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 5 years of experience with physical design flows and methodologies (RTL2GDS).
  • Experience with semiconductor process technologies (deep submicron, advanced nodes like 5nm and below), and device physics (MOSFET/FINFET).
  • Experience with design for testability (DFT) and low-power design methodologies.
  • Experience with UPF (Unified Power Format) and its application in physical design.
Preferred qualifications:
  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  • Experience with scripting languages such as Perl, Python, or Tcl.
  • Excellent analysis skills, with the ability to understand, debug, and resolve issues in the design flow.
About the job:

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities:
  • Develop and optimize the overall layout of the chip, including partitioning, macro and IP placement, and pin placement.
  • Design and implement efficient power delivery networks (power grids) to ensure stable power to all parts of the chip.
  • Develop and validate high-performance, low-power clock networks (Clock Tree Synthesis - CTS) to ensure proper synchronization across the entire chip.
  • Develop, enhance, and maintain custom scripts (e.g., Tcl, Perl, Python) for automation and improved efficiency.
  • Conduct extensive design rule checks (DRC) to ensure the layout adheres to manufacturing rules, performing layout versus schematic (LVS) checks to verify that the physical layout matches the logical design.

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