CPU Logic Design Engineer, Cloud, PhD, University Graduate, Start 2025

1 week ago

Haifa, Haifa, Israel Google Full time ₪90,000 - ₪120,000 per year

Note: By applying to this position you will have an opportunity to share your preferred working location from the following:
Haifa, Israel; Tel Aviv, Israel
.
Minimum qualifications:

  • PhD degree Electrical Engineering or Computer Science, or equivalent practical experience.
  • Experience digital logic at Register Transfer Level (RTL) level using SystemVerilog or VHDL.

Preferred qualifications:

  • Experience in Design/microarchitecture.

About The Job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

The ML, Systems & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud's Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

Responsibilities

  • Contribute to CPU frontend designs, emphasizing on microarchitecture and RTL design for the next generation CPU.
  • Propose performance enhancing microarchitecture features with efficiency in mind. Work with architects and performance teams for trade-off studies. Communicate pros and cons of microarchitecture enhancements. Facilitate final decision making.
  • Deliver designs meeting Power, performance, and area (PPA) goals with production quality.
  • Become familiar with techniques for at least one processor functional block. Interpret the techniques into design constructs and languages in order to provide guidance to and participate in the performance modeling effort.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .

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