DFx Validation Engineer

Job Details
Job Description:

• About our Organization: P-Core (Performance Core)

We are designing the future of compute

We develop Intel's main and most valuable & complex IP – the Performance-CORE. It is the central part of many Intel's products: Desktops, Notebooks, Servers, Cloud CPUs, AI solutions and more.

Our CORE is in the heart of hundreds of millions of products being sold every year, and is driving the internet, AI, networking industry, cloud compute, communications, consumers and more.

About the team: Design For Test (DFT) Team
The P-Core DFT Team owns the architectural definition, logic design and verification of the DFT infrastructure, features and flows in the P-Core.

Our mission is to drive qualitative and timely DFT deployment on P-Core projects while ensuring high coverage to reduce DPM (Defects Per Million) and efficient HVM (High Volume Manufacturing) testing mechanisms to support TTR (Test Time Reduction), as well as define future DFT methodology.

We work jointly with all the functional design and verification engineers in the P-Core, and collaborate closely with the post-silicon product engineers, as well as the SoC engineers of the products which consume P-Core.

We are a newly formed team with a growing scope and plenty of room to grow, while ensuring great technical mentorship by experts in the DFT field.

DFT is a fascinating arena which involves all aspects of design and process technology and offers a unique opportunity to be a key part throughout a project's life cycle.

About The Job

• Design, code, simulate and integrate DFT blocks (including TAP, SCAN, MBIST, etc.) into functional logic and ensure their high-quality integration.
• Participate in the definition of CPU architecture and microarchitecture features to make sure they are covered by DFT.
• Provide DFT test content generation and delivery to manufacturing for various DFT content.
• Develop HVM (High Volume Manufacturing) content for rapid bring up and ramp to production on the automatic test equipment (ATE).
• Ensure DFT design features are verified correctly and resolve and implement corrective measures for failing RTL tests to assure features quality.
• Optimize logic to qualify the design to meet DPM and test-time goals.
• Collaborate with post-silicon and manufacturing team to verify the feature on silicon, support debug requirements, and apply learnings on future products.

Qualifications

• B.Sc. or M.Sc. in Electrical Engineering or Computer Engineering.
• At least 5 years of experience in hardware and logic verification or design.
• Self and fast learner with good problem-solving capabilities.
• Good communication skills and Fluent English (written and oral).
• Experience with Post-silicon debug and content generation - advantage.
• Scripting abilities (Perl/Python/Tcl) and Unix familiarity - advantage.
• Design for Test (DFT) Flows, Tools and Technique - advantage.

Job Type
Experienced Hire

Shift
Shift 1 (Israel)

Primary Location:

Israel, Haifa

Additional Locations:

Business Group
The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them.

Posting Statement
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.