Junior SoC IP Design Engineer, Cloud

1 week ago

Haifa, Haifa, Israel Google Full time $150,000 - $200,000 per year

Note: By applying to this position you will have an opportunity to share your preferred working location from the following:
Tel Aviv, Israel; Haifa, Israel
.
Minimum qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 1 year of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
  • Experience with design sign off and quality tools (Lint , CDC , etc.).

Preferred qualifications:

  • Master's or PhD in Computer Science or related technical fields.
  • Knowledge in one of these areas: PCIe, UCIe, DDR, AXI, ARM processors family.
  • Knowledge of high performance and low power design techniques.
  • Knowledge of assertion-based formal verification.
  • Knowledge of SOC architecture.
  • Excellent problem-solving and debugging skills.

About The Job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud's Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

Responsibilities

  • Define the SoC/Block level design document such as interface protocol, block diagram, transaction flow, pipeline etc.
  • Perform RTL development (coding and debug in Verilog, SystemVerilog), function/performance simulation debug and Lint/CDC/FV/UPF checks.
  • Participate in synthesis, timing/power closure and ASIC silicon bring-up.
  • Participate in test plan and coverage analysis of the block and SOC-level verification.
  • Communicate and work with multi-disciplined and multi-site teams.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .

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