Senior Architectural Designer

6 hours ago

Caesarea, Haifa, Israel AI-Fabrics Full time ₪120,000 - ₪180,000 per year

Senior Architecture & Performance Modeling Engineer - Silicon

A unique opportunity to take part in building a new Israeli R&D site from the ground up. We are looking for highly experienced, top-tier talents and visionary silicon architects to drive the development of advanced
AI connectivity and networking architectures
, shaping the site's technological foundation and long-term innovation.

Responsibilities

  • Own the development of
    architecture and performance models
    for next-generation AI fabric - interconnect, memory systems, and networking pipelines.
  • Define and evaluate hardware and system architecture from concept to production, influencing key design decisions.
  • Analyze workloads, traffic patterns, and scaling behavior to identify bottlenecks and optimize performance across the silicon architecture.
  • Build, validate, and maintain high-fidelity simulation frameworks and tools (SystemC/C++/Python or equivalent).
  • Collaborate closely with RTL, micro-architecture, verification, physical design, and software teams to ensure performance targets and architectural intent are met.
  • Contribute to the definition of IP and SoC architecture for innovative Switch, NIC, and distributed AI connectivity products.
  • Act as a key contributor in shaping the technological direction, methodologies, and culture of the new Israeli site.

Requirements

  • 10+ years
    of hands-on experience in architecture modeling, performance modeling, or silicon/system architecture.
  • B.Sc. in Electrical Engineering, Computer Engineering, or Computer Science –
    required
    .
  • M.Sc. or Ph.D. –
    advantage
    .
  • Proven track record in designing or modeling
    high-performance, scalable digital systems
    (SoC, fabric, memory hierarchy, compute units).
  • Strong background in system architecture concepts such as NoC/fabric, cache/memory subsystems, traffic shaping, and throughput/latency analysis.
  • Hands-on experience with modeling tools and environments:
    SystemC, C++, Python
    , cycle-accurate or trace-driven simulators.
  • Experience with Networking, Switch/NIC architectures, or AI workloads –
    Required
  • Familiarity with ASIC development flows and collaboration interfaces with RTL, verification, and physical design.
  • Strong leadership, ownership, and ability to drive complex architecture initiatives independently.
  • Excellent communication skills and fluency in English.

Location Caesarea (Walking distance from Train station)

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