Experienced Full Chip Timing Designer

2 weeks ago

PTK PTK Petah Tikva, Israel Intel Full time ₪120,000 - ₪180,000 per year
Job Details:Job Description: 

Performs timing analysis and timing optimization, generates, and verifies timing constraints, and fixes timing violations at chip/block level for SoCs. Conducts timing rollups, designs for functionality, and develops performance and power optimized clock networks. Develops and defines methodologies to ensure highest quality of timing models that enable the physical design team to operate efficiently. Defines the right process, voltage, and temperature (PVT) conditions to be used for timing analysis for a given design based on the product plans such as operating conditions and binning. Works closely with the clocking team and other backend full chip designers for clocking balance, timing fixes, power delivery, and partitioning. Collaborates with architecture, clocking design, and logic design teams to deliver flow development for chip integration and validates high performance low power clock network guidelines.

About the Team

The Full Chip Timing (FCT) Design Automation team plays a critical role in supporting all aspects of full chip timing integration. Our mission is to enable seamless timing closure and optimization across the entire backend flow. We develop and maintain automation environments, tools, and methodologies that ensure high-quality timing models and constraint management.

Qualifications:

What you will do:

  • Build and maintain automation environments for timing model generation
  • Support backend platforms to resolve timing violations
  • Drive timing closure across physical design stages
  • Innovate with AI-based tools, indicators, and ad-hoc automation
  • Own constraint management and budgeting flows using top high end CAD tools

What we are looking for:

  • BSC Electronics Engineering or a related field
  • 5+ years of experience in scripting and software development (TCL, Python, AI-based coding tools).
  • Deep knowledge of backend design: synthesis, place & route (P&R), STA (Primetime preferred)
  • Hands-on experience with optimization flows of STA tools
  • Proactive, self-driven mindset with strong ownership attitude
  • Customer-focused and collaborative team player
  • Curious, innovative, and eager to push boundaries

    #GrowWithIntel
Job Type:Experienced HireShift:Shift 1 (Israel)Primary Location: Israel, Petah-TikvaAdditional Locations:Business group:The Silicon Engineering Group (SIG) is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs from architecture to manufacturing readiness that power Intel's leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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