Custom Silicon Solutions Architect

2 days ago

Tel AvivYafo, Israel beBeeDesign Full time
Senior ASIC and IP Designer

We are seeking a highly skilled Senior ASIC and IP Designer to join our team. The ideal candidate will have extensive experience in digital logic design, RTL coding, and low-power design techniques.

Job Description

This role involves the development of custom silicon solutions for Google's direct-to-consumer products. You will be responsible for creating SoC level micro architecture definitions, RTL coding, and all RTL quality checks.

Required Skills and Qualifications
  • Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
  • 8 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
  • Experience in logic synthesis techniques to optimize RTL code, performance, and power.
  • Experience with design sign off and quality tools.
Preferred Qualifications
  • Master's degree or PhD in Computer Science or a related technical field.
  • Knowledge of assertion-based formal verification.
  • Knowledge in one of these areas: PCIe, UCIe, DDR, AXI, ARM processors family.
  • Excellent problem solving and debugging skills.
About the Role

You will be part of a team that develops the ASIC SoC from POR to Production. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will collaborate with members of architecture, software, verification, power, timing, synthesis DFT etc. You will face technical tests and develop/design options for performance, power, and area.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing.

Responsibilities
  • Define the SoC/Block level design document.
  • Perform Register-Transfer Level (RTL) development.
  • Participate in synthesis, timing/power closure, and Application-Specific Integrated Circuit (ASIC) silicon bring-up.
  • Participate in test plan and coverage analysis of the block and SOC-level verification.

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